jishu0.qsf

Verilog 实现9999计数

# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		jishu0_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name FAMILY "MAX II"
set_global_assignment -name DEVICE EPM240T100C5
set_global_assignment -name TOP_LEVEL_ENTITY Block1
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 6.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:43:47  JANUARY 15, 2008"
set_global_assignment -name LAST_QUARTUS_VERSION 6.0
set_global_assignment -name VERILOG_FILE jishu0.v
set_global_assignment -name VECTOR_WAVEFORM_FILE jishu0.vwf
set_global_assignment -name VERILOG_FILE yima.v
set_global_assignment -name VERILOG_FILE dis.v
set_global_assignment -name VERILOG_FILE fegpin.v
set_global_assignment -name VERILOG_FILE fengpin1.v
set_global_assignment -name BDF_FILE Block1.bdf
set_global_assignment -name VERILOG_FILE mux.v
set_global_assignment -name VERILOG_FILE dispselect.v
set_global_assignment -name VERILOG_FILE fen1hz.v
set_global_assignment -name VERILOG_FILE fen1k.v
set_location_assignment PIN_15 -to q[0]
set_location_assignment PIN_16 -to q[1]
set_location_assignment PIN_17 -to q[2]
set_location_assignment PIN_18 -to q[3]
set_location_assignment PIN_19 -to q[4]
set_location_assignment PIN_20 -to q[5]
set_location_assignment PIN_21 -to q[6]
set_location_assignment PIN_26 -to q[7]
set_location_assignment PIN_1 -to d_out[0]
set_location_assignment PIN_2 -to d_out[1]
set_global_assignment -name VERILOG_FILE ji.v
set_location_assignment PIN_3 -to d_out[2]
set_global_assignment -name VERILOG_FILE jishu1.v
set_location_assignment PIN_4 -to d_out[3]
set_location_assignment PIN_5 -to d_out[4]
set_location_assignment PIN_12 -to clk_in0