dis.v

来自「Verilog 实现9999计数」· Verilog 代码 · 共 11 行

module dis(clk2,q2);
input clk2;
output q2;
reg q2;
integer wo;
always@(posedge clk2)
    if(wo==9)
    q2<=1;
   else
    q2<=0;
 endmodule