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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity or_fd is
generic(
init_val : string := "0";
no : integer := 0;
yes : integer := 1
);
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity and_a_b is
generic(
no : integer := 0;
yes : integer := 1
);
port(
a_in : in
anal.info
file {
.version = 1;
entity {
.name = "module_c";
.mra_file = "module_c.mra";
.arch = {"verilog"};
.syn_files = {"module_c%verilog.syn", "module_c%verilog__verilog.syn"};
prescale_counter.versim_par
prescale_counter.versim_par -- generated only for ProjNav status tracking
Simulation Model Target: Generic_Verilog
ram_single_port_128x8.tlg
Selecting top level module ram_single_port_128x8
Synthesizing module ram_single_port_128x8
@N: CL134 :"D:\CD\hdl_example_v2_synplify\spro_703\verilog\ram\default\ram_single_port_128x8.v":60:11:60:19
xstdemo_vlog_prj.gfl
# Verilog : PDCL (jhdparse)
__projnav/cnt_vlog_jhdparse_tcl.rsp
# Verilog : PDCL (jhdparse)
__projnav/cnt_vlog_jhdparse_tcl.rsp
# Check Syntax
cnt_vlog.stx
# xst flow : RunXST
cnt_vlog.syr
cnt
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity alu is
port(
clk : in vl_logic;
a : in vl_logic_vector(7 downto 0);
b : in
case3s.v
//*********************************************************
// IEEE STD 1364-1995 Verilog file: case3s.v
// Author-EMAIL: Uwe.Meyer-Baese@ieee.org
//************************************************
case3s.v
//*********************************************************
// IEEE STD 1364-1995 Verilog file: case3s.v
// Author-EMAIL: Uwe.Meyer-Baese@ieee.org
//************************************************
lfsr.v
//*********************************************************
// IEEE STD 1364-1995 Verilog file: lfsr.v
// Author-EMAIL: Uwe.Meyer-Baese@ieee.org
//**************************************************