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delay_vhd_synthesis.nlf
Release 8.2i - netgen I.31
Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
Command Line: netgen -intstyle ise -insert_glbl true -w -dir netgen/synthesis
-ofmt verilog -sim DELAY_VHD.ngc D
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity rom is
port(
data : out vl_logic_vector(7 downto 0);
addr : in vl_logic_vector(12 downto 0);
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity alu is
generic(
HLT : integer := 0;
SKZ : integer := 1;
ADD : integer := 2;
\A
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ram is
port(
data : inout vl_logic_vector(7 downto 0);
addr : in vl_logic_vector(9 downto 0);
e
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity accum is
port(
accum : out vl_logic_vector(7 downto 0);
data : in vl_logic_vector(7 downto 0);
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity glbl is
generic(
ROC_WIDTH : integer := 100000;
TOC_WIDTH : integer := 0
);
end glbl;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity glbl is
generic(
ROC_WIDTH : integer := 100000;
TOC_WIDTH : integer := 0
);
end glbl;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity glbl is
generic(
roc_width : integer := 100000;
toc_width : integer := 0
);
end glbl;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity glbl is
generic(
ROC_WIDTH : integer := 100000;
TOC_WIDTH : integer := 0
);
end glbl;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ccmul is
generic(
w2 : integer := 17;
w1 : integer := 9;
w : integer := 8
);