_primary.vhd

精简CPU设计

library verilog;
use verilog.vl_types.all;
entity rom is
    port(
        data            : out    vl_logic_vector(7 downto 0);
        addr            : in     vl_logic_vector(12 downto 0);
        read            : in     vl_logic;
        ena             : in     vl_logic
    );
end rom;