_primary.vhd

精简CPU设计

library verilog;
use verilog.vl_types.all;
entity ram is
    port(
        data            : inout  vl_logic_vector(7 downto 0);
        addr            : in     vl_logic_vector(9 downto 0);
        ena             : in     vl_logic;
        read            : in     vl_logic;
        write           : in     vl_logic
    );
end ram;