代码搜索结果
找到约 10,000 项符合
Verilog 的代码
prev_cmp_usb2_v.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}
prev_cmp_usb2_v.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}
prev_cmp_usb2_v.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}
prev_cmp_usb2_v.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity glbl is
generic(
roc_width : integer := 100000;
toc_width : integer := 0
);
end glbl;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity front is
port(
clk_5m : in vl_logic;
rst : in vl_logic;
nd : in vl_logic;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity pingpang is
port(
clk_5m : in vl_logic;
rst : in vl_logic;
nd : in vl_logic;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity SK is
port(
rst : in vl_logic;
ack_in : in vl_logic;
din_3 : in vl_logic_vector
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity receive is
port(
clk : in vl_logic;
req_in : in vl_logic;
ack_out : out vl_logic
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity receiver is
port(
clk : in vl_logic;
req_in : in vl_logic;
ack_out : out vl_logic