prev_cmp_usb2_v.map.qmsg

USB2_V例子工程是一个FPGA数据通过USB2.0传输到PC机的示例.

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Create Symbol File Quartus II " "Info: Running Quartus II Create Symbol File" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version " "Info: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon May 18 11:47:23 2009 " "Info: Processing started: Mon May 18 11:47:23 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off USB2_V -c USB2_V --generate_symbol=E:\\wt\\workspace\\mywork\\USB2_V\\usb_port.v " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off USB2_V -c USB2_V --generate_symbol=E:\\wt\\workspace\\mywork\\USB2_V\\usb_port.v" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IVRFX_L3_HDL_OBJECT_DECLARED_NOT_USED" "R2 usb_port.v(63) " "Info (10035): Verilog HDL or VHDL information at usb_port.v(63): object \"R2\" declared but not used" {  } { { "usb_port.v" "" { Text "E:/wt/workspace/mywork/USB2_V/usb_port.v" 63 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 1 0 "" 0}
{ "Info" "IVRFX_L3_HDL_OBJECT_DECLARED_NOT_USED" "R3 usb_port.v(63) " "Info (10035): Verilog HDL or VHDL information at usb_port.v(63): object \"R3\" declared but not used" {  } { { "usb_port.v" "" { Text "E:/wt/workspace/mywork/USB2_V/usb_port.v" 63 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 1 0 "" 0}
{ "Info" "IVRFX_L3_HDL_OBJECT_DECLARED_NOT_USED" "W2 usb_port.v(63) " "Info (10035): Verilog HDL or VHDL information at usb_port.v(63): object \"W2\" declared but not used" {  } { { "usb_port.v" "" { Text "E:/wt/workspace/mywork/USB2_V/usb_port.v" 63 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 1 0 "" 0}
{ "Info" "IVRFX_L3_HDL_OBJECT_DECLARED_NOT_USED" "W3 usb_port.v(63) " "Info (10035): Verilog HDL or VHDL information at usb_port.v(63): object \"W3\" declared but not used" {  } { { "usb_port.v" "" { Text "E:/wt/workspace/mywork/USB2_V/usb_port.v" 63 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 1 0 "" 0}
{ "Info" "IVRFX_L3_HDL_OBJECT_DECLARED_NOT_USED" "W4 usb_port.v(63) " "Info (10035): Verilog HDL or VHDL information at usb_port.v(63): object \"W4\" declared but not used" {  } { { "usb_port.v" "" { Text "E:/wt/workspace/mywork/USB2_V/usb_port.v" 63 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 1 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Create Symbol File 0 s 0 s Quartus II " "Info: Quartus II Create Symbol File was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "135 " "Info: Allocated 135 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon May 18 11:47:23 2009 " "Info: Processing ended: Mon May 18 11:47:23 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}