_primary.vhd

来自「自己写一个关于维mesh结构的noc网络」· VHDL 代码 · 共 10 行

library verilog;
use verilog.vl_types.all;
entity receive is
    port(
        clk             : in     vl_logic;
        req_in          : in     vl_logic;
        ack_out         : out    vl_logic
    );
end receive;