_primary.vhd

来自「自己写一个关于维mesh结构的noc网络」· VHDL 代码 · 共 10 行

library verilog;
use verilog.vl_types.all;
entity SSC is
    port(
        req_c           : in     vl_logic;
        did             : in     vl_logic_vector(2 downto 0);
        req             : out    vl_logic_vector(4 downto 0)
    );
end SSC;