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dump.vcd
$date
Mon Jul 24 20:52:49 2006
$end
$version
Icarus Verilog
$end
$timescale
10ps
$end
$scope module testbench $end
$var reg 1 ! clk $end
$var reg 4 " ins_len[3:0] $end
$var reg 8 # ip_n
reset.hif
Version 7.2 Build 151 09/26/2007 SJ Full Version
38
2265
OFF
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Path
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity glbl is
generic(
ROC_WIDTH : integer := 100000;
TOC_WIDTH : integer := 0
);
end glbl;
lin.tan.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus
makefile
all: sim
SHELL = /bin/sh
#MS=-s
##########################################################################
#
# DUT Sources
#
#########################################################################
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity main_test is
port(
clk : out vl_logic;
reset : out vl_logic
);
end main_test;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity glbl is
generic(
roc_width : integer := 100000;
toc_width : integer := 0
);
end glbl;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity alu is
port(
clk : in vl_logic;
a : in vl_logic_vector(7 downto 0);
b : in
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity m3s011br is
port(
clk : in vl_logic;
nrst : in vl_logic;
ccr : in vl_logic_
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity mi2c is
port(
clk : in vl_logic;
nrst : in vl_logic;
a : in vl_logic_vect