_primary.vhd

来自「altera i2c host/device」· VHDL 代码 · 共 12 行

library verilog;
use verilog.vl_types.all;
entity m3s011br is
    port(
        clk             : in     vl_logic;
        nrst            : in     vl_logic;
        ccr             : in     vl_logic_vector(6 downto 0);
        clkenab         : out    vl_logic;
        maclkenab       : out    vl_logic
    );
end m3s011br;