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library verilog; use verilog.vl_types.all; entity mux_x is port( i : in vl_logic_vector(2 downto 0); x_i : out vl_logic_vector(7 downto 0);

library verilog; use verilog.vl_types.all; entity Dff is port( clk : in vl_logic; reset : in vl_logic; D : in vl_logic_vecto

library verilog; use verilog.vl_types.all; entity wallce_tree is port( x : in vl_logic_vector(8 downto 0); h : in vl_logic_vector(7 downto 0);

library verilog; use verilog.vl_types.all; entity booth_code is port( b : in vl_logic_vector(2 downto 0); x : in vl_logic_vector(8 downto 0);

library verilog; use verilog.vl_types.all; entity add_8b is port( a : in vl_logic_vector(7 downto 0); b : in vl_logic_vector(7 downto 0);

library verilog; use verilog.vl_types.all; entity add_20b is port( a : in vl_logic_vector(16 downto 0); b : in vl_logic_vector(18 downto 0);

library verilog; use verilog.vl_types.all; entity glbl is generic( roc_width : integer := 100000; toc_width : integer := 0 ); end glbl;

verilog work i2c_master_bit_ctrl.v verilog work i2c_master_byte_ctrl.v verilog work i2c_master_top.v

library verilog; use verilog.vl_types.all; entity glbl is generic( roc_width : integer := 100000; toc_width : integer := 0 ); end glbl;

Version 8.1 Build 163 10/28/2008 SJ Full Version 7 530 OFF OFF OFF OFF ON ON ON FV_OFF Level2 0 0 VRSM_ON VHSM_ON 0 -- Start Partition -- -- End Partition -- -- Start Library Paths