_primary.vhd

来自「fpga功能实现有限字长响应FIR 用verilog编写」· VHDL 代码 · 共 10 行

library verilog;
use verilog.vl_types.all;
entity wallce_tree is
    port(
        x               : in     vl_logic_vector(8 downto 0);
        h               : in     vl_logic_vector(7 downto 0);
        \out\           : out    vl_logic_vector(16 downto 0)
    );
end wallce_tree;