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Verilog 的代码
shifter_2.v
//
// Verilog Module final_year_proj_lib.shifter_2.arch_name
//
// Created:
// by - admin.UNKNOWN (LENOVO-7FE010A7)
// at - 23:42:04 02/21/2008
//
// using Mentor Graphics HDL Design
shifter_4.v
//
// Verilog Module final_year_proj_lib.shifter_4.arch_name
//
// Created:
// by - admin.UNKNOWN (LENOVO-7FE010A7)
// at - 23:59:50 02/21/2008
//
// using Mentor Graphics HDL Design
ping_tb.f
/***********************************************************************
File: ping_tb.f
Rev: 3.0.0
This file contains the input arguments for the Verilog simulator.
Copyright (c) 200
voptmmr6nz
library verilog;
use verilog.vl_types.all;
entity DPLL is
port(
clock : in vl_logic;
reset : in vl_logic;
Fin : in vl_logic;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity rom is
port(
aclr : in vl_logic;
address : in vl_logic_vector(7 downto 0);
clock : in
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity Reset_Delay is
port(
iCLK : in vl_logic;
oRESET : out vl_logic
);
end Reset_Delay;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity SEG7_LUT_4 is
port(
oSEG0 : out vl_logic_vector(6 downto 0);
oSEG1 : out vl_logic_vector(6 downto 0);
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity SRAM_16Bit_512K is
port(
oDATA : out vl_logic_vector(15 downto 0);
iDATA : in vl_logic_vector(15 downto
read.scr
read -format vhdl verilog/new/ALARM_BLOCK.vhd
read -format vhdl verilog/new/ALARM_SM_2.vhd
read -format vhdl verilog/new/CLOCK_GEN.vhd
read -format vhdl verilog/new/COMPARATOR.vhd
read -format vhdl ve
pulse_16_sum.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Qua