shifter_4.v

it is used to find traffic

//
// Verilog Module final_year_proj_lib.shifter_4.arch_name
//
// Created:
//          by - admin.UNKNOWN (LENOVO-7FE010A7)
//          at - 23:59:50 02/21/2008
//
// using Mentor Graphics HDL Designer(TM) 2004.1b (Build 12)
//
`resetall
`timescale 1ns/10ps
module shifter_4(in,out);
  input [23:0] in;
  output[23:0] out;
  wire [23:0] out;
assign  out={2'b0,in[23:2]};
// ### Please start your Verilog code here ###
endmodule