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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity fpgab_top is
generic(
Uncode : integer := 0;
Code12 : integer := 1;
Code34 : integer := 2
)
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity pn_test is
generic(
PERIOD : integer := 200;
DUTY_CYCLE : real := 0.500000;
OFFSET : integer :=
pngenchuan_18.hif
Version 7.2 Build 151 09/26/2007 SJ Full Version
11
1029
OFF
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Path
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity glbl is
generic(
roc_width : integer := 100000;
toc_width : integer := 0
);
end glbl;
i2c_master_top.prj
verilog work i2c_master_bit_ctrl.v
verilog work i2c_master_byte_ctrl.v
verilog work i2c_master_top.v
psp.hif
Version 7.1 Build 156 04/30/2007 SJ Full Version
37
2133
OFF
OFF
OFF
OFF
ON
ON
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Pat
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity glbl is
generic(
roc_width : integer := 100000;
toc_width : integer := 0
);
end glbl;
i2c_master_top.prj
verilog work i2c_master_bit_ctrl.v
verilog work i2c_master_byte_ctrl.v
verilog work i2c_master_top.v
row_proc_tb.v
//
// Verilog Module dwt_final_lib.row_proc_tb.arch_name
//
// Created:
// by - VLSI4.UNKNOWN (VLSI04)
// at - 10:43:40 03/29/2008
//
// using Mentor Graphics HDL Designer(TM) 2004.1
cla_24.v
//
// Verilog Module dwt2_lib.cla_24.arch_name
//
// Created:
// by - VLSI4.UNKNOWN (VLSI04)
// at - 10:54:21 02/20/2008
//
// using Mentor Graphics HDL Designer(TM) 2004.1b (Build 1