cla_24.v

it is used to find traffic

//
// Verilog Module dwt2_lib.cla_24.arch_name
//
// Created:
//          by - VLSI4.UNKNOWN (VLSI04)
//          at - 10:54:21 02/20/2008
//
// using Mentor Graphics HDL Designer(TM) 2004.1b (Build 12)
//
`resetall
`timescale 1ns/10ps
module cla_24(in1,in2,out_sum,out_carry);
  
  input [23:0] in1,in2;  
  output [23:0] out_sum;
  output out_carry;
  
  wire [23:0] in1,in2,out_sum;
  wire out_carry;
  wire int_carry1,int_carry2,int_carry3,int_carry4,int_carry5;
  
  cla_4 cla1(in1[3:0],in2[3:0],1'b0,out_sum[3:0],int_carry1);
  cla_4 cla2(in1[7:4],in2[7:4],int_carry1,out_sum[7:4],int_carry2);
  cla_4 cla3(in1[11:8],in2[11:8],int_carry2,out_sum[11:8],int_carry3);
  cla_4 cla4(in1[15:12],in2[15:12],int_carry3,out_sum[15:12],int_carry4);
  cla_4 cla5(in1[19:16],in2[19:16],int_carry4,out_sum[19:16],int_carry5);
  cla_4 cla6(in1[23:20],in2[23:20],int_carry5,out_sum[23:20],out_carry);
  
  
//if we perform subtraction such that in2 is larger than in1 then we need to check the borrow bit and perform twos complement of output)
// ### Please start your Verilog code here ###
endmodule