row_proc_tb.v

it is used to find traffic

//
// Verilog Module dwt_final_lib.row_proc_tb.arch_name
//
// Created:
//          by - VLSI4.UNKNOWN (VLSI04)
//          at - 10:43:40 03/29/2008
//
// using Mentor Graphics HDL Designer(TM) 2004.1b (Build 12)
//
`resetall
`timescale 1ns/10ps
module row_proc_tb;
  
  reg [23:0] in1,in2;
  reg clock,reset;
  wire [23:0] out1,out2;
  
  initial 
  begin
    clock=1'b0;
    reset=1'b0;
    in1=24'b000000000010000000000000;
    in2=24'b000000000010000000000000;
    #2 reset=1'b1;
    #3 reset=1'b0;
    #6 reset=1'b1;
    #2 reset=1'b0;
    #3 reset=1'b1;
  end
  
  always
    #5 clock=!clock;

 //always
//  begin
//    #10 in1=~in1;
//    #15 in2=~in2;
//  end
 
 row_proc rp(in1,in2,clock,reset,Ext_en1,Ext_en2,Ext_en3,Ext_en4,sel_en,out1,out2);
 fsm fsm1(clock,reset,Ext_en1,Ext_en2,Ext_en3,Ext_en4,sel_en);

// ### Please start your Verilog code here ###
endmodule