代码搜索：Verilog
找到约 10,000 项符合「Verilog」的源代码
代码结果 10,000
www.eeworm.com/read/235010/14088992
cmd_log ddr_command.cmd_log
xst -intstyle ise -ifn __projnav/ddr_command.xst -ofn ddr_command.syr
xst -intstyle ise -ifn __projnav/ddr_command.xst -ofn ddr_command.syr
ngdbuild -intstyle ise -dd f:\ise_test/_ngo -i -p xc2s200
www.eeworm.com/read/235010/14089019
par_nlf ddr_command.par_nlf
Release 6.2i - netgen G.28
Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.
Loading device database for application netgen from file "ddr_command.ncd".
"ddr_command" is an NCD, version 2
www.eeworm.com/read/235010/14089050
gfl ise_test.gfl
# XST (Creating Lso File) :
ddr_command.lso
# xst flow : RunXST
ddr_command.syr
ddr_command.prj
ddr_command.sprj
ddr_command.ana
ddr_command.stx
ddr_command.cmd_log
ddr_command.ngc
ddr_comm
www.eeworm.com/read/202015/15391141
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity and16 is
port(
y : out vl_logic_vector(15 downto 0);
in1 : in vl_logic_vector(15 downto 0)
);
www.eeworm.com/read/192379/8384448
pdf 第四章 不同抽象级别的verilog hdl模型.pdf
www.eeworm.com/read/389296/8534339
pdf 第四章 不同抽象级别的verilog hdl模型.pdf
www.eeworm.com/read/289446/8550618
doc 通用串行异步收发器8251的verilog hdl源代码.doc
www.eeworm.com/read/418996/10889877
pdf 基于verilog_hdl的uart串行通讯模块设计及仿真.pdf
www.eeworm.com/read/409718/11315248
doc 第 6讲 用verilog.做cpld的设计doc.doc
www.eeworm.com/read/124648/14555451