代码搜索：Verilog
找到约 10,000 项符合「Verilog」的源代码
代码结果 10,000
www.eeworm.com/read/159314/5585629
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity fdce is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q :
www.eeworm.com/read/159314/5585630
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ilflx is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q :
www.eeworm.com/read/159314/5585632
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity fdrse is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q :
www.eeworm.com/read/159314/5585636
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvcmos18_s_8 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in
www.eeworm.com/read/159314/5585651
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity fddrrse is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q
www.eeworm.com/read/159314/5585652
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ilflx_1m is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q
www.eeworm.com/read/159314/5585660
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvcmos2 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_l
www.eeworm.com/read/159314/5585662
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity fdcpe is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q :
www.eeworm.com/read/159314/5585666
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity oor2 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i0
www.eeworm.com/read/159314/5585669
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvcmos25_s_6 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in