_primary.vhd

来自「Xilinx的modelsim 仿真库！里面有许多库函数」· VHDL 代码 · 共 17 行

library verilog;
use verilog.vl_types.all;
entity fdcpe is
    generic(
        cds_action      : string  := "ignore";
        init            : integer := 0
    );
    port(
        q               : out    vl_logic;
        c               : in     vl_logic;
        ce              : in     vl_logic;
        clr             : in     vl_logic;
        d               : in     vl_logic;
        pre             : in     vl_logic
    );
end fdcpe;