代码搜索：Verilog
找到约 10,000 项符合「Verilog」的源代码
代码结果 10,000
www.eeworm.com/read/159314/5584975
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_s_16 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_logi
www.eeworm.com/read/159314/5584984
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ram64x2s is
generic(
cds_action : string := "ignore";
init_00 : integer := 0;
init_01 : integer := 0
www.eeworm.com/read/159314/5584985
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ildxi_1m is
generic(
cds_action : string := "ignore";
init : integer := 1
);
port(
q
www.eeworm.com/read/159314/5584990
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity nor12 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i0
www.eeworm.com/read/159314/5584993
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity fdrs is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q :
www.eeworm.com/read/159314/5584995
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvcmos18 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_
www.eeworm.com/read/159314/5584996
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity or4b3 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i0
www.eeworm.com/read/159314/5585000
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity nor4 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i0
www.eeworm.com/read/159314/5585015
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity muxf6_l is
generic(
cds_action : string := "ignore"
);
port(
lo : out vl_logic;
i0
www.eeworm.com/read/159314/5585018
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvpecl is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_lo