_primary.vhd

来自「Xilinx的modelsim 仿真库！里面有许多库函数」· VHDL 代码 · 共 23 行

library verilog;
use verilog.vl_types.all;
entity nor12 is
    generic(
        cds_action      : string  := "ignore"
    );
    port(
        o               : out    vl_logic;
        i0              : in     vl_logic;
        i1              : in     vl_logic;
        i2              : in     vl_logic;
        i3              : in     vl_logic;
        i4              : in     vl_logic;
        i5              : in     vl_logic;
        i6              : in     vl_logic;
        i7              : in     vl_logic;
        i8              : in     vl_logic;
        i9              : in     vl_logic;
        i10             : in     vl_logic;
        i11             : in     vl_logic
    );
end nor12;