_primary.vhd

来自「Xilinx的modelsim 仿真库！里面有许多库函数」· VHDL 代码 · 共 24 行

library verilog;
use verilog.vl_types.all;
entity ram64x2s is
    generic(
        cds_action      : string  := "ignore";
        init_00         : integer := 0;
        init_01         : integer := 0
    );
    port(
        o0              : out    vl_logic;
        o1              : out    vl_logic;
        a0              : in     vl_logic;
        a1              : in     vl_logic;
        a2              : in     vl_logic;
        a3              : in     vl_logic;
        a4              : in     vl_logic;
        a5              : in     vl_logic;
        d0              : in     vl_logic;
        d1              : in     vl_logic;
        wclk            : in     vl_logic;
        we              : in     vl_logic
    );
end ram64x2s;