代码搜索：Verilog
找到约 10,000 项符合「Verilog」的源代码
代码结果 10,000
www.eeworm.com/read/347114/11693433
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity altgxb_l40 is
port(
l40_out : out vl_logic;
a : in vl_logic;
b : in vl_logi
www.eeworm.com/read/347114/11693441
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity altgxb_l31 is
port(
l31_out : out vl_logic;
a : in vl_logic;
b : in vl_logi
www.eeworm.com/read/347114/11693453
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity altgxb_t11 is
port(
t11_out : out vl_logic;
a : in vl_logic;
b : in vl_logi
www.eeworm.com/read/347114/11693474
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity pll_reg is
port(
q : out vl_logic;
clk : in vl_logic;
ena : in vl_logic;
www.eeworm.com/read/347114/11693525
_info
m255
cModel Technology
dD:\quartus_30\quartus\tpi\mgc_oem
vand1
IbX`i3
VzNO3AF7X_1hjETK^b?5423
d.
FQuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/hcstratix_atoms.v)
L0 222
OV;L
www.eeworm.com/read/347114/11693689
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity and16 is
port(
\Y\ : out vl_logic_vector(15 downto 0);
\IN1\ : in vl_logic_vector(15 downto 0)
);
www.eeworm.com/read/347114/11693782
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity pll_reg is
port(
q : out vl_logic;
clk : in vl_logic;
ena : in vl_logic;
www.eeworm.com/read/347114/11693972
_info
m255
cModel Technology
dD:\quartus_30\quartus\tpi\mgc_oem
vAND1
I5QbEGUY4LPF__LOC09K
www.eeworm.com/read/347114/11699277
_info
m255
cModel Technology
dD:\quartus_30\quartus\tpi\mgc_oem
vand1
VzNO3AF7X_1hjETK^b?5423
r1
31
OE;L;5.6;17
IbX`i3
d.
FQuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_at
www.eeworm.com/read/347114/11699527
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity and16 is
port(
\Y\ : out vl_logic_vector(15 downto 0);
\IN1\ : in vl_logic_vector(15 downto 0)
);