代码搜索：Verilog
找到约 10,000 项符合「Verilog」的源代码
代码结果 10,000
www.eeworm.com/read/347114/11692811
_info
m255
cModel Technology
dD:\quartus_30\quartus\tpi\mgc_oem
vand1
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r1
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d.
FQuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_at
www.eeworm.com/read/347114/11693076
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity and16 is
port(
\Y\ : out vl_logic_vector(15 downto 0);
\IN1\ : in vl_logic_vector(15 downto 0)
);
www.eeworm.com/read/347114/11693121
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity pll_reg is
port(
q : out vl_logic;
clk : in vl_logic;
ena : in vl_logic;
www.eeworm.com/read/347114/11693203
_info
m255
cModel Technology
dD:\quartus_30\quartus\tpi\mgc_oem
valtgxb
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V`mobi
www.eeworm.com/read/347114/11693235
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity altgxb_t02 is
port(
t02_out : out vl_logic;
a : in vl_logic;
b : in vl_logi
www.eeworm.com/read/347114/11693275
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity altgxb_l13 is
port(
l13_out : out vl_logic;
a : in vl_logic;
b : in vl_logi
www.eeworm.com/read/347114/11693308
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity altgxb_t20 is
port(
t20_out : out vl_logic;
a : in vl_logic;
b : in vl_logi
www.eeworm.com/read/347114/11693336
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity altgxb_l22 is
port(
l22_out : out vl_logic;
a : in vl_logic;
b : in vl_logi
www.eeworm.com/read/347114/11693365
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity mux4 is
port(
\Y\ : out vl_logic;
\I0\ : in vl_logic;
\I1\ : in vl_logic;
www.eeworm.com/read/347114/11693375
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity altgxb_l04 is
port(
l04_out : out vl_logic;
a : in vl_logic;
b : in vl_logi