代码搜索：Verilog
找到约 10,000 项符合「Verilog」的源代码
代码结果 10,000
www.eeworm.com/read/330799/12868554
qmsg sram_control.fnsim.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "I
www.eeworm.com/read/330798/12868625
qsf fir.qsf
# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
www.eeworm.com/read/140218/13096054
out quartus_map.out
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 4.2 Build 156 11/29/2004 SJ Web Edition
Info: Copyright
www.eeworm.com/read/324339/13271155
qsf de2_i2sound.qsf
# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any
www.eeworm.com/read/137348/13327151
in int2bin.in
///
/// created by oc8051 rom maker
/// author: Simon Teran (simont@opencores.org)
///
/// source file: D:\verilog\oc8051\test\int2bin.hex
/// date: 19.6.02
/// time: 10:15:04
///
02
00
2E
www.eeworm.com/read/321790/13398941
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratix_jtag is
generic(
lpm_type : string := "stratix_jtag"
);
port(
tms : in vl_logic;
t
www.eeworm.com/read/321790/13398977
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity carry_sum is
port(
sin : in vl_logic;
cin : in vl_logic;
sout : out vl_logic
www.eeworm.com/read/321790/13399058
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity hcstratix_jtag is
generic(
lpm_type : string := "hcstratix_jtag"
);
port(
tms : in vl_logic;
www.eeworm.com/read/321790/13399067
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity and16 is
port(
y : out vl_logic_vector(15 downto 0);
in1 : in vl_logic_vector(15 downto 0)
);
www.eeworm.com/read/321790/13399124
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity pll_reg is
port(
q : out vl_logic;
clk : in vl_logic;
ena : in vl_logic;