📄 sram_control.fnsim.qmsg
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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Functional Simulation Netlist Generation Quartus II " "Info: Running Quartus II Functional Simulation Netlist Generation" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" { } { } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Jul 07 13:52:15 2007 " "Info: Processing started: Sat Jul 07 13:52:15 2007" { } { } 0 0 "Processing started: %1!s!" 0 0} } { } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off sram_control -c sram_control --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off sram_control -c sram_control --generate_functional_sim_netlist" { } { } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WVRFX_VERI_XZ_EXTEND_SIGNIFICANT" "sram_control.v(64) " "Warning (10273): Verilog HDL warning at sram_control.v(64): extended using \"x\" or \"z\"" { } { { "sram_control.v" "" { Text "F:/fpga test/sram_control/sram_control.v" 64 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0}
{ "Warning" "WVRFX_VERI_XZ_EXTEND_SIGNIFICANT" "sram_control.v(65) " "Warning (10273): Verilog HDL warning at sram_control.v(65): extended using \"x\" or \"z\"" { } { { "sram_control.v" "" { Text "F:/fpga test/sram_control/sram_control.v" 65 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0}
{ "Warning" "WVRFX_VERI_XZ_EXTEND_SIGNIFICANT" "sram_control.v(66) " "Warning (10273): Verilog HDL warning at sram_control.v(66): extended using \"x\" or \"z\"" { } { { "sram_control.v" "" { Text "F:/fpga test/sram_control/sram_control.v" 66 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sram_control.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file sram_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 sram_control " "Info: Found entity 1: sram_control" { } { { "sram_control.v" "" { Text "F:/fpga test/sram_control/sram_control.v" 1 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0} } { } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "sram_control " "Info: Elaborating entity \"sram_control\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "datardbuf sram_control.v(40) " "Warning (10036): Verilog HDL or VHDL warning at sram_control.v(40): object \"datardbuf\" assigned a value but never read" { } { { "sram_control.v" "" { Text "F:/fpga test/sram_control/sram_control.v" 40 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 sram_control.v(73) " "Warning (10230): Verilog HDL assignment warning at sram_control.v(73): truncated value with size 32 to match size of target (1)" { } { { "sram_control.v" "" { Text "F:/fpga test/sram_control/sram_control.v" 73 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 sram_control.v(74) " "Warning (10230): Verilog HDL assignment warning at sram_control.v(74): truncated value with size 32 to match size of target (1)" { } { { "sram_control.v" "" { Text "F:/fpga test/sram_control/sram_control.v" 74 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 sram_control.v(75) " "Warning (10230): Verilog HDL assignment warning at sram_control.v(75): truncated value with size 32 to match size of target (1)" { } { { "sram_control.v" "" { Text "F:/fpga test/sram_control/sram_control.v" 75 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 sram_control.v(90) " "Warning (10230): Verilog HDL assignment warning at sram_control.v(90): truncated value with size 32 to match size of target (1)" { } { { "sram_control.v" "" { Text "F:/fpga test/sram_control/sram_control.v" 90 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 sram_control.v(91) " "Warning (10230): Verilog HDL assignment warning at sram_control.v(91): truncated value with size 32 to match size of target (1)" { } { { "sram_control.v" "" { Text "F:/fpga test/sram_control/sram_control.v" 91 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 sram_control.v(92) " "Warning (10230): Verilog HDL assignment warning at sram_control.v(92): truncated value with size 32 to match size of target (1)" { } { { "sram_control.v" "" { Text "F:/fpga test/sram_control/sram_control.v" 92 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 sram_control.v(125) " "Warning (10230): Verilog HDL assignment warning at sram_control.v(125): truncated value with size 32 to match size of target (1)" { } { { "sram_control.v" "" { Text "F:/fpga test/sram_control/sram_control.v" 125 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 sram_control.v(138) " "Warning (10230): Verilog HDL assignment warning at sram_control.v(138): truncated value with size 32 to match size of target (1)" { } { { "sram_control.v" "" { Text "F:/fpga test/sram_control/sram_control.v" 138 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 sram_control.v(139) " "Warning (10230): Verilog HDL assignment warning at sram_control.v(139): truncated value with size 32 to match size of target (1)" { } { { "sram_control.v" "" { Text "F:/fpga test/sram_control/sram_control.v" 139 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 sram_control.v(145) " "Warning (10230): Verilog HDL assignment warning at sram_control.v(145): truncated value with size 32 to match size of target (1)" { } { { "sram_control.v" "" { Text "F:/fpga test/sram_control/sram_control.v" 145 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 sram_control.v(146) " "Warning (10230): Verilog HDL assignment warning at sram_control.v(146): truncated value with size 32 to match size of target (1)" { } { { "sram_control.v" "" { Text "F:/fpga test/sram_control/sram_control.v" 146 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 17 sram_control.v(162) " "Warning (10230): Verilog HDL assignment warning at sram_control.v(162): truncated value with size 32 to match size of target (17)" { } { { "sram_control.v" "" { Text "F:/fpga test/sram_control/sram_control.v" 162 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
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