quartus_map.out

CPLD的VerilogHDL总线代码,在EPM7128SLC84-10+Quartus4平台上运行通过.

Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.2 Build 156 11/29/2004 SJ Web Edition
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    Info: Processing started: Fri Jul 29 16:26:43 2005
Info: Command: quartus_map cpld_bus -c cpld_bus
Warning: Verilog HDL expression warning at decode.v(17): truncated literal to match 2 bits
Warning: Verilog HDL expression warning at decode.v(18): truncated literal to match 2 bits
Warning: Verilog HDL expression warning at decode.v(19): truncated literal to match 2 bits
Warning: Verilog HDL expression warning at decode.v(20): truncated literal to match 2 bits
Info: Found 1 design units, including 1 entities, in source file decode.v
    Info: Found entity 1: decode
Info: Found 1 design units, including 1 entities, in source file cpld_bus.bdf
    Info: Found entity 1: cpld_bus
Info: Found 1 design units, including 1 entities, in source file bus_ISM.v
    Info: Found entity 1: bus_ISM
Warning: Verilog HDL warning at data_out_mux.v(10): using previously specified range for net, port, or variable "reg_en"
Error: Verilog HDL syntax error at data_out_mux.v(14) near text "and";  expecting ")", or binary operator,  File: E:/project/cpld_bus/data_out_mux.v Line: 14
Error: Ignored module "Data_Out_Mux" at data_out_mux.v(1) because of previous errors File: E:/project/cpld_bus/data_out_mux.v Line: 1
Info: Found 0 design units, including 0 entities, in source file data_out_mux.v
Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 5 warnings
    Error: Processing ended: Fri Jul 29 16:26:43 2005
    Error: Elapsed time: 00:00:01