代码搜索：Verilog
找到约 10,000 项符合「Verilog」的源代码
代码结果 10,000
www.eeworm.com/read/448726/7526499
var hdl.var
# hdl.var file
#
# Version 1a, 1 June 04
#
# Olaf Zinke
#
# Downloaded from The Designer's Guide (www.designers-guide.org).
# Post any questions on www.designers-guide.org/Forum.
# Taken from "The Des
www.eeworm.com/read/448726/7526503
lib cds.lib
# cds.lib file
#
# Version 1a, 1 June 04
#
# Olaf Zinke
#
# Downloaded from The Designer's Guide (www.designers-guide.org).
# Post any questions on www.designers-guide.org/Forum.
# Taken from "The Des
www.eeworm.com/read/447899/7544268
qsf ps2.qsf
# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
www.eeworm.com/read/447899/7544296
qmsg ps2.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "I
www.eeworm.com/read/447896/7544414
qmsg lcd_1602.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "I
www.eeworm.com/read/447893/7544500
qmsg beep.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "I
www.eeworm.com/read/297875/7990833
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity decode4_7 is
port(
decodeout : out vl_logic_vector(6 downto 0);
indec : in vl_logic_vector(3 downto 0)
www.eeworm.com/read/398207/7999743
qmsg beep.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "I
www.eeworm.com/read/297692/8004193
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity and16 is
port(
y : out vl_logic_vector(15 downto 0);
in1 : in vl_logic_vector(15 downto 0)
);
www.eeworm.com/read/245183/12812390
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity reg1 is
port(
\in\ : in vl_logic;
\out\ : out vl_logic;
clk : in vl_logic