_primary.vhd

verilog源代码 王金明教程用的配套代码和一些可综合代码

library verilog;
use verilog.vl_types.all;
entity decode4_7 is
    port(
        decodeout       : out    vl_logic_vector(6 downto 0);
        indec           : in     vl_logic_vector(3 downto 0)
    );
end decode4_7;