lcd_1602.map.qmsg

液晶1602驱动并显示

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version " "Info: Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Nov 23 21:27:13 2006 " "Info: Processing started: Thu Nov 23 21:27:13 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off lcd_1602 -c lcd_1602 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lcd_1602 -c lcd_1602" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lcd_1602.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file lcd_1602.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 lcd_1602 " "Info: Found entity 1: lcd_1602" {  } { { "lcd_1602.bdf" "" { Schematic "D:/lcd_1602/lcd_1602.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WVRFX_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "lcd.v(98) " "Warning (10268): Verilog HDL information at lcd.v(98): Always Construct contains both blocking and non-blocking assignments" {  } { { "lcd.v" "" { Text "D:/lcd_1602/lcd.v" 98 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lcd.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file lcd.v" { { "Info" "ISGN_ENTITY_NAME" "1 lcd " "Info: Found entity 1: lcd" {  } { { "lcd.v" "" { Text "D:/lcd_1602/lcd.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "char_ram.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file char_ram.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 char_ram-fun " "Info: Found design unit 1: char_ram-fun" {  } { { "char_ram.vhd" "" { Text "D:/lcd_1602/char_ram.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 char_ram " "Info: Found entity 1: char_ram" {  } { { "char_ram.vhd" "" { Text "D:/lcd_1602/char_ram.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "lcd_1602 " "Info: Elaborating entity \"lcd_1602\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lcd lcd:inst " "Info: Elaborating entity \"lcd\" for hierarchy \"lcd:inst\"" {  } { { "lcd_1602.bdf" "inst" { Schematic "D:/lcd_1602/lcd_1602.bdf" { { 24 288 400 152 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "READFLAG lcd.v(36) " "Warning (10036): Verilog HDL or VHDL warning at lcd.v(36): object \"READFLAG\" assigned a value but never read" {  } { { "lcd.v" "" { Text "D:/lcd_1602/lcd.v" 36 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "READRAM lcd.v(38) " "Warning (10036): Verilog HDL or VHDL warning at lcd.v(38): object \"READRAM\" assigned a value but never read" {  } { { "lcd.v" "" { Text "D:/lcd_1602/lcd.v" 38 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "cur_dec lcd.v(41) " "Warning (10036): Verilog HDL or VHDL warning at lcd.v(41): object \"cur_dec\" assigned a value but never read" {  } { { "lcd.v" "" { Text "D:/lcd_1602/lcd.v" 41 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "cur_shift lcd.v(42) " "Warning (10036): Verilog HDL or VHDL warning at lcd.v(42): object \"cur_shift\" assigned a value but never read" {  } { { "lcd.v" "" { Text "D:/lcd_1602/lcd.v" 42 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "shift_cur lcd.v(48) " "Warning (10036): Verilog HDL or VHDL warning at lcd.v(48): object \"shift_cur\" assigned a value but never read" {  } { { "lcd.v" "" { Text "D:/lcd_1602/lcd.v" 48 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "right_shift lcd.v(49) " "Warning (10036): Verilog HDL or VHDL warning at lcd.v(49): object \"right_shift\" assigned a value but never read" {  } { { "lcd.v" "" { Text "D:/lcd_1602/lcd.v" 49 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "datawidth4 lcd.v(52) " "Warning (10036): Verilog HDL or VHDL warning at lcd.v(52): object \"datawidth4\" assigned a value but never read" {  } { { "lcd.v" "" { Text "D:/lcd_1602/lcd.v" 52 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "oneline lcd.v(54) " "Warning (10036): Verilog HDL or VHDL warning at lcd.v(54): object \"oneline\" assigned a value but never read" {  } { { "lcd.v" "" { Text "D:/lcd_1602/lcd.v" 54 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "font5x7 lcd.v(56) " "Warning (10036): Verilog HDL or VHDL warning at lcd.v(56): object \"font5x7\" assigned a value but never read" {  } { { "lcd.v" "" { Text "D:/lcd_1602/lcd.v" 56 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 21 lcd.v(71) " "Warning (10230): Verilog HDL assignment warning at lcd.v(71): truncated value with size 32 to match size of target (21)" {  } { { "lcd.v" "" { Text "D:/lcd_1602/lcd.v" 71 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(75) " "Warning (10230): Verilog HDL assignment warning at lcd.v(75): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "D:/lcd_1602/lcd.v" 75 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}