代码搜索：Verilog
找到约 10,000 项符合「Verilog」的源代码
代码结果 10,000
www.eeworm.com/read/468753/6987441
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity bitwise_or is
port(
in1 : in vl_logic_vector(31 downto 0);
in2 : in vl_logic_vector(31 downto 0);
www.eeworm.com/read/468066/6998889
qsf mulfactor.qsf
# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
www.eeworm.com/read/464849/7060924
prj test_pwm_sch_beh.prj
verilog work "cntr4.v"
verilog work "mag4comp.v"
verilog work "pwm_sch.vf"
verilog work "test_pwm_sch.tfw"
verilog work C:/Xilinx/verilog/src/glbl.v
www.eeworm.com/read/464849/7060993
isim_beh_prj test_pwm_sch.isim_beh_prj
verilog work "cntr4.v"
verilog work "mag4comp.v"
verilog work "pwm_sch.vf"
verilog work "test_pwm_sch.tfw"
verilog work C:/Xilinx/verilog/src/glbl.v
www.eeworm.com/read/465033/7064420
qsf shifter.qsf
# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
www.eeworm.com/read/465036/7064680
qsf alu.qsf
# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
www.eeworm.com/read/426573/7088358
qsf edge.qsf
# Copyright (C) 1991-2008 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
www.eeworm.com/read/340731/7107343
qmsg clock.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info:
www.eeworm.com/read/340731/7107390
qmsg clock.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info:
www.eeworm.com/read/264839/7110859
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity half_add1 is
port(
a : in vl_logic;
b : in vl_logic;
sum : out vl_logic