📄 clock.map.qmsg
字号:
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" { } { } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Feb 18 13:48:05 2006 " "Info: Processing started: Sat Feb 18 13:48:05 2006" { } { } 0} } { } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off clock -c clock " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off clock -c clock" { } { } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clock.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file clock.v" { { "Info" "ISGN_ENTITY_NAME" "1 clock " "Info: Found entity 1: clock" { } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 4 -1 0 } } } 0} } { } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "clock " "Info: Elaborating entity \"clock\" for the top level hierarchy" { } { } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 clock.v(18) " "Warning: Verilog HDL assignment warning at clock.v(18): truncated value with size 32 to match size of target (1)" { } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 18 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 clock.v(19) " "Warning: Verilog HDL assignment warning at clock.v(19): truncated value with size 32 to match size of target (1)" { } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 19 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 clock.v(20) " "Warning: Verilog HDL assignment warning at clock.v(20): truncated value with size 32 to match size of target (1)" { } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 20 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 clock.v(21) " "Warning: Verilog HDL assignment warning at clock.v(21): truncated value with size 32 to match size of target (1)" { } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 21 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 clock.v(22) " "Warning: Verilog HDL assignment warning at clock.v(22): truncated value with size 32 to match size of target (1)" { } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 22 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 clock.v(23) " "Warning: Verilog HDL assignment warning at clock.v(23): truncated value with size 32 to match size of target (1)" { } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 23 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 clock.v(28) " "Warning: Verilog HDL assignment warning at clock.v(28): truncated value with size 32 to match size of target (16)" { } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 28 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 clock.v(32) " "Warning: Verilog HDL assignment warning at clock.v(32): truncated value with size 32 to match size of target (16)" { } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 32 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 26 clock.v(67) " "Warning: Verilog HDL assignment warning at clock.v(67): truncated value with size 32 to match size of target (26)" { } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 67 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 26 clock.v(69) " "Warning: Verilog HDL assignment warning at clock.v(69): truncated value with size 32 to match size of target (26)" { } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 69 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 26 clock.v(71) " "Warning: Verilog HDL assignment warning at clock.v(71): truncated value with size 32 to match size of target (26)" { } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 71 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(77) " "Warning: Verilog HDL assignment warning at clock.v(77): truncated value with size 32 to match size of target (4)" { } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 77 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(78) " "Warning: Verilog HDL assignment warning at clock.v(78): truncated value with size 32 to match size of target (4)" { } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 78 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(79) " "Warning: Verilog HDL assignment warning at clock.v(79): truncated value with size 32 to match size of target (4)" { } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 79 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(80) " "Warning: Verilog HDL assignment warning at clock.v(80): truncated value with size 32 to match size of target (4)" { } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 80 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(81) " "Warning: Verilog HDL assignment warning at clock.v(81): truncated value with size 32 to match size of target (4)" { } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 81 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(82) " "Warning: Verilog HDL assignment warning at clock.v(82): truncated value with size 32 to match size of target (4)" { } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 82 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(83) " "Warning: Verilog HDL assignment warning at clock.v(83): truncated value with size 32 to match size of target (4)" { } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 83 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(84) " "Warning: Verilog HDL assignment warning at clock.v(84): truncated value with size 32 to match size of target (4)" { } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 84 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(89) " "Warning: Verilog HDL assignment warning at clock.v(89): truncated value with size 32 to match size of target (4)" { } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 89 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(91) " "Warning: Verilog HDL assignment warning at clock.v(91): truncated value with size 32 to match size of target (4)" { } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 91 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(93) " "Warning: Verilog HDL assignment warning at clock.v(93): truncated value with size 32 to match size of target (4)" { } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 93 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(95) " "Warning: Verilog HDL assignment warning at clock.v(95): truncated value with size 32 to match size of target (4)" { } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 95 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(97) " "Warning: Verilog HDL assignment warning at clock.v(97): truncated value with size 32 to match size of target (4)" { } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 97 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(99) " "Warning: Verilog HDL assignment warning at clock.v(99): truncated value with size 32 to match size of target (4)" { } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 99 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(101) " "Warning: Verilog HDL assignment warning at clock.v(101): truncated value with size 32 to match size of target (4)" { } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 101 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(103) " "Warning: Verilog HDL assignment warning at clock.v(103): truncated value with size 32 to match size of target (4)" { } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 103 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(105) " "Warning: Verilog HDL assignment warning at clock.v(105): truncated value with size 32 to match size of target (4)" { } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 105 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(107) " "Warning: Verilog HDL assignment warning at clock.v(107): truncated value with size 32 to match size of target (4)" { } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 107 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(109) " "Warning: Verilog HDL assignment warning at clock.v(109): truncated value with size 32 to match size of target (4)" { } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 109 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(111) " "Warning: Verilog HDL assignment warning at clock.v(111): truncated value with size 32 to match size of target (4)" { } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 111 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "dataout_buf\[2\] clock.v(74) " "Warning: Verilog HDL Always Construct warning at clock.v(74): variable \"dataout_buf\[2\]\" may not be assigned a new value in every possible path through the Always Construct. Variable \"dataout_buf\[2\]\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." { } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 74 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "dataout_buf\[5\] clock.v(74) " "Warning: Verilog HDL Always Construct warning at clock.v(74): variable \"dataout_buf\[5\]\" may not be assigned a new value in every possible path through the Always Construct. Variable \"dataout_buf\[5\]\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." { } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 74 0 0 } } } 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" { } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 9 -1 0 } } { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 9 -1 0 } } { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 9 -1 0 } } { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 9 -1 0 } } { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 9 -1 0 } } { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 9 -1 0 } } { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 9 -1 0 } } { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 12 -1 0 } } { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 12 -1 0 } } } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "192 " "Info: Implemented 192 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" { } { } 0} { "Info" "ISCL_SCL_TM_OPINS" "16 " "Info: Implemented 16 output pins" { } { } 0} { "Info" "ISCL_SCL_TM_LCELLS" "174 " "Info: Implemented 174 logic cells" { } { } 0} } { } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 33 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 33 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Feb 18 13:48:10 2006 " "Info: Processing ended: Sat Feb 18 13:48:10 2006" { } { } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" { } { } 0} } { } 0}
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -