代码搜索：Verilog
找到约 10,000 项符合「Verilog」的源代码
代码结果 10,000
www.eeworm.com/read/276511/10733141
voptz5swmz
library verilog;
use verilog.vl_types.all;
entity id_counter is
port(
IDclock : in vl_logic;
reset : in vl_logic;
inc : in vl_logi
www.eeworm.com/read/276511/10733153
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity id_counter is
port(
IDclock : in vl_logic;
reset : in vl_logic;
inc : in vl_logi
www.eeworm.com/read/420528/10791588
rpt fifo.map.rpt
Analysis & Synthesis report for FIFO
Thu Jul 03 15:44:23 2008
Quartus II Version 8.0 Build 215 05/29/2008 SJ Full Version
---------------------
; Table of Contents ;
---------------------
www.eeworm.com/read/420528/10791654
qsf fifo.qsf
# Copyright (C) 1991-2008 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
www.eeworm.com/read/349305/10836668
_info
m255
13
cModel Technology
dG:\verilog\LCDtest\LCD_top
vReset_Delay
Im2=nAg]:[65Wg[D;46Q9U3
VDoL>1[=KXh_Qfl1[=KX
www.eeworm.com/read/349305/10836725
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity SEG7_LUT is
port(
oSEG : out vl_logic_vector(6 downto 0);
iDIG : in vl_logic_vector(3 downto 0)
)
www.eeworm.com/read/348886/10861606
smsg config_dac.map.smsg
Warning (10236): Verilog HDL Implicit Net warning at ad9777_spi_interface.v(43): created implicit net for "lsb_fist"
www.eeworm.com/read/273951/10893859
qmsg gate_control.tan.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus
www.eeworm.com/read/468753/6987207
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity bitwise_and is
port(
in1 : in vl_logic_vector(31 downto 0);
in2 : in vl_logic_vector(31 downto 0);
www.eeworm.com/read/468753/6987399
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity bitwise_not is
port(
\in\ : in vl_logic_vector(31 downto 0);
\out\ : out vl_logic_vector(31 downto 0)