_primary.vhd

来自「一个实现简单的数字锁相环Verilog代码」· VHDL 代码 · 共 12 行

library verilog;
use verilog.vl_types.all;
entity id_counter is
    port(
        IDclock         : in     vl_logic;
        reset           : in     vl_logic;
        inc             : in     vl_logic;
        dec             : in     vl_logic;
        IDout           : out    vl_logic
    );
end id_counter;