代码搜索：Verilog
找到约 10,000 项符合「Verilog」的源代码
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www.eeworm.com/read/152144/12136050
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity test is
generic(
CLK_CYCLE : integer := 488
);
end test;
www.eeworm.com/read/152049/12148611
rpt key_scan1.map.rpt
Analysis & Synthesis report for key_scan1
Mon Sep 05 19:26:16 2005
Version 5.0 Build 148 04/26/2005 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Leg
www.eeworm.com/read/340417/12160189
qmsg dispselect.tan.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus
www.eeworm.com/read/340417/12161314
qmsg dispdecoder.tan.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus
www.eeworm.com/read/253978/12171229
qsf top_pci32.qsf
# Copyright (C) 1991-2004 Altera Corporation
# Any megafunction design, and related netlist (encrypted or decrypted),
# support information, device programming or simulation file, and any oth
www.eeworm.com/read/151836/12171576
qsf top_pci32.qsf
# Copyright (C) 1991-2004 Altera Corporation
# Any megafunction design, and related netlist (encrypted or decrypted),
# support information, device programming or simulation file, and any oth
www.eeworm.com/read/150866/12254618
transcript
# Reading C:/Modeltech_6.0c/tcl/vsim/pref.tcl
# // ModelSim SE 6.0c Feb 2 2005
# //
# // Copyright Mentor Graphics Corporation 2005
# // All Rights Reserved.
# //
# // THIS WO
www.eeworm.com/read/132039/14113247
prj mix_scr.prj
#-- Synplicity, Inc.
#-- Version 7.2
#-- Project file J:\temp\Synplify_Pro\Mix\Mix_scr.prj
#-- Written on Thu Dec 19 18:06:58 2002
#add_file options
add_file -vhdl -lib work "cslt_cnt
www.eeworm.com/read/233546/14147585
smsg uart_regs.map.smsg
Warning (10236): Verilog HDL Implicit Net warning at uart_regs.v(115): created implicit net for "rf_overrun"
www.eeworm.com/read/130914/14167598
fld tiny16_maxii.fld
c:/otherquartusprojects/processor/verilog/tiny16/db/tiny16_MAXII.quartus_db
tiny16_MAXII
sgroom
V1