mix_scr.prj

Verilog&Vhdl混语言对SDRAM的控制源代码

#-- Synplicity, Inc.
#-- Version 7.2        
#-- Project file J:\temp\Synplify_Pro\Mix\Mix_scr.prj
#-- Written on Thu Dec 19 18:06:58 2002


#add_file options
add_file -vhdl -lib work "cslt_cntr.vhd"
add_file -vhdl -lib work "mti_pkg.vhd"
add_file -vhdl -lib work "rcd_cntr.vhd"
add_file -vhdl -lib work "sdrmc_state.vhd"
add_file -vhdl -lib work "sdrm_t.vhd"
add_file -verilog "brst_cntr.v"
add_file -verilog "ki_cntr.v"
add_file -verilog "ref_cntr.v"
add_file -verilog "sys_int.v"
add_file -verilog "define.v"
add_file -verilog "xilinx_lib/virtexe.v"
add_file -verilog "sdrm.v"


#implementation: "rev_1"
impl -add rev_1

#device options
set_option -technology VIRTEX-E
set_option -part XCV400E
set_option -package BG560
set_option -speed_grade -7

#compilation/mapping options
set_option -default_enum_encoding default
set_option -symbolic_fsm_compiler 1
set_option -resource_sharing 0
set_option -use_fsm_explorer 0
set_option -top_module "sdrm"

#map options
set_option -frequency 125.000
set_option -fanout_limit 100
set_option -disable_io_insertion 0
set_option -pipe 1
set_option -update_models_cp 0
set_option -verification_mode 0
set_option -modular 0
set_option -retiming 1

#simulation options
set_option -write_verilog 0
set_option -write_vhdl 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "rev_1/sdrm.edf"

#implementation attributes
set_option -vlog_std v2001
set_option -compiler_compatible 0
set_option -include_path "J:/eda/synplicity/Synplify_72/lib/xilinx/"
impl -active "rev_1"