dispdecoder.tan.qmsg

频率计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jul 17 22:27:30 2006 " "Info: Processing started: Mon Jul 17 22:27:30 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off dispdecoder -c dispdecoder " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off dispdecoder -c dispdecoder" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "data_out\[0\]\$latch~10 " "Info: Node \"data_out\[0\]\$latch~10\"" {  } { { "dispdecoder.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/dispdecoder/dispdecoder.v" 30 -1 0 } }  } 0}  } { { "dispdecoder.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/dispdecoder/dispdecoder.v" 30 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "data_out\[1\]\$latch~10 " "Info: Node \"data_out\[1\]\$latch~10\"" {  } { { "dispdecoder.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/dispdecoder/dispdecoder.v" 30 -1 0 } }  } 0}  } { { "dispdecoder.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/dispdecoder/dispdecoder.v" 30 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "data_out\[2\]\$latch~10 " "Info: Node \"data_out\[2\]\$latch~10\"" {  } { { "dispdecoder.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/dispdecoder/dispdecoder.v" 30 -1 0 } }  } 0}  } { { "dispdecoder.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/dispdecoder/dispdecoder.v" 30 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "data_out\[3\]\$latch~10 " "Info: Node \"data_out\[3\]\$latch~10\"" {  } { { "dispdecoder.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/dispdecoder/dispdecoder.v" 30 -1 0 } }  } 0}  } { { "dispdecoder.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/dispdecoder/dispdecoder.v" 30 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "data_out\[4\]\$latch~10 " "Info: Node \"data_out\[4\]\$latch~10\"" {  } { { "dispdecoder.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/dispdecoder/dispdecoder.v" 30 -1 0 } }  } 0}  } { { "dispdecoder.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/dispdecoder/dispdecoder.v" 30 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "data_out\[5\]\$latch~10 " "Info: Node \"data_out\[5\]\$latch~10\"" {  } { { "dispdecoder.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/dispdecoder/dispdecoder.v" 30 -1 0 } }  } 0}  } { { "dispdecoder.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/dispdecoder/dispdecoder.v" 30 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "data_out\[6\]\$latch~10 " "Info: Node \"data_out\[6\]\$latch~10\"" {  } { { "dispdecoder.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/dispdecoder/dispdecoder.v" 30 -1 0 } }  } 0}  } { { "dispdecoder.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/dispdecoder/dispdecoder.v" 30 -1 0 } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "dp_s10hz data_out\[0\] 9.800 ns Longest " "Info: Longest tpd from source pin \"dp_s10hz\" to destination pin \"data_out\[0\]\" is 9.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns dp_s10hz 1 PIN PIN_29 3 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_29; Fanout = 3; PIN Node = 'dp_s10hz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/dispdecoder/db/dispdecoder_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/dispdecoder/db/dispdecoder_cmp.qrpt" Compiler "dispdecoder" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/dispdecoder/db/dispdecoder.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/dispdecoder/" "" "" { dp_s10hz } "NODE_NAME" } "" } } { "dispdecoder.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/dispdecoder/dispdecoder.v" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(3.500 ns) 4.900 ns hide~363 2 COMB LC34 21 " "Info: 2: + IC(1.200 ns) + CELL(3.500 ns) = 4.900 ns; Loc. = LC34; Fanout = 21; COMB Node = 'hide~363'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/dispdecoder/db/dispdecoder_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/dispdecoder/db/dispdecoder_cmp.qrpt" Compiler "dispdecoder" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/dispdecoder/db/dispdecoder.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/dispdecoder/" "" "4.700 ns" { dp_s10hz hide~363 } "NODE_NAME" } "" } } { "dispdecoder.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/dispdecoder/dispdecoder.v" 20 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.700 ns) 9.600 ns data_out\[0\]\$latch~10 3 COMB LOOP LC4 3 " "Info: 3: + IC(0.000 ns) + CELL(4.700 ns) = 9.600 ns; Loc. = LC4; Fanout = 3; COMB LOOP Node = 'data_out\[0\]\$latch~10'" { { "Info" "ITDB_PART_OF_SCC" "data_out\[0\]\$latch~10 LC4 " "Info: Loc. = LC4; Node \"data_out\[0\]\$latch~10\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/dispdecoder/db/dispdecoder_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/dispdecoder/db/dispdecoder_cmp.qrpt" Compiler "dispdecoder" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/dispdecoder/db/dispdecoder.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/dispdecoder/" "" "" { data_out[0]$latch~10 } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/dispdecoder/db/dispdecoder_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/dispdecoder/db/dispdecoder_cmp.qrpt" Compiler "dispdecoder" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/dispdecoder/db/dispdecoder.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/dispdecoder/" "" "" { data_out[0]$latch~10 } "NODE_NAME" } "" } } { "dispdecoder.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/dispdecoder/dispdecoder.v" 30 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/dispdecoder/db/dispdecoder_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/dispdecoder/db/dispdecoder_cmp.qrpt" Compiler "dispdecoder" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/dispdecoder/db/dispdecoder.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/dispdecoder/" "" "4.700 ns" { hide~363 data_out[0]$latch~10 } "NODE_NAME" } "" } } { "dispdecoder.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/dispdecoder/dispdecoder.v" 30 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 9.800 ns data_out\[0\] 4 PIN PIN_10 0 " "Info: 4: + IC(0.000 ns) + CELL(0.200 ns) = 9.800 ns; Loc. = PIN_10; Fanout = 0; PIN Node = 'data_out\[0\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/dispdecoder/db/dispdecoder_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/dispdecoder/db/dispdecoder_cmp.qrpt" Compiler "dispdecoder" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/dispdecoder/db/dispdecoder.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/dispdecoder/" "" "0.200 ns" { data_out[0]$latch~10 data_out[0] } "NODE_NAME" } "" } } { "dispdecoder.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/dispdecoder/dispdecoder.v" 9 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.600 ns 87.76 % " "Info: Total cell delay = 8.600 ns ( 87.76 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.200 ns 12.24 % " "Info: Total interconnect delay = 1.200 ns ( 12.24 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/dispdecoder/db/dispdecoder_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/dispdecoder/db/dispdecoder_cmp.qrpt" Compiler "dispdecoder" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/dispdecoder/db/dispdecoder.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/dispdecoder/" "" "9.800 ns" { dp_s10hz hide~363 data_out[0]$latch~10 data_out[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "9.800 ns" { dp_s10hz dp_s10hz~out hide~363 data_out[0]$latch~10 data_out[0] } { 0.000ns 0.000ns 1.200ns 0.000ns 0.000ns } { 0.000ns 0.200ns 3.500ns 4.700ns 0.200ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Jul 17 22:27:31 2006 " "Info: Processing ended: Mon Jul 17 22:27:31 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}