代码搜索：Verilog
找到约 10,000 项符合「Verilog」的源代码
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www.eeworm.com/read/478173/6721004
vppreproc
#!/usr/bin/perl -w
# See copyright, etc in below POD section.
######################################################################
require 5.005;
use lib 'blib/arch';
use lib 'blib/lib';
use lib '.
www.eeworm.com/read/477743/6733661
cfg compxlib.cfg
#*****************************************************************
# compxlib initialization file (compxlib.cfg) *
#
www.eeworm.com/read/410651/11273296
qmsg ps2.fit.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "I
www.eeworm.com/read/408281/11400050
qmsg ps2.fit.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "I
www.eeworm.com/read/405399/11463373
qmsg prev_cmp_alltest.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}
www.eeworm.com/read/404187/11490589
qsf top_pci32.qsf
# Copyright (C) 1991-2004 Altera Corporation
# Any megafunction design, and related netlist (encrypted or decrypted),
# support information, device programming or simulation file, and any oth
www.eeworm.com/read/403293/11519764
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity wb_conbusex_top_bench is
end wb_conbusex_top_bench;
www.eeworm.com/read/403293/11519777
vopt8sdani
library verilog;
use verilog.vl_types.all;
entity wb_conbusex_top_bench is
end wb_conbusex_top_bench;
www.eeworm.com/read/402169/11541538
txt icunit_beschreibung.txt
NAME
icunit - Management of ICPRO design units
SYNOPSIS
icunit [-OPTION] [-VIEW] [-HDL]
-VIEW : -rtl | -beh | -tb
-HDL : -verilog | -systemverilog
www.eeworm.com/read/347114/11690458
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity and1 is
port(
\Y\ : out vl_logic;
\IN1\ : in vl_logic
);
end and1;