prev_cmp_alltest.map.qmsg

EPM1270下的 LED闪烁程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Create Symbol File Quartus II " "Info: Running Quartus II Create Symbol File" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jan 15 11:27:54 2009 " "Info: Processing started: Thu Jan 15 11:27:54 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off AllTest -c AllTest --generate_symbol=LCD1602.v " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off AllTest -c AllTest --generate_symbol=LCD1602.v" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "LCD1602.v(112) " "Warning (10268): Verilog HDL information at LCD1602.v(112): Always Construct contains both blocking and non-blocking assignments" {  } { { "LCD1602.v" "" { Text "D:/Nailson/MCU/CPLD/AllTest/LCD1602.v" 112 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0 "" 0}
{ "Info" "IVRFX_L3_HDL_OBJECT_DECLARED_NOT_USED" "READFLAG LCD1602.v(50) " "Info (10035): Verilog HDL or VHDL information at LCD1602.v(50): object \"READFLAG\" declared but not used" {  } { { "LCD1602.v" "" { Text "D:/Nailson/MCU/CPLD/AllTest/LCD1602.v" 50 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 1 0 "" 0}
{ "Info" "IVRFX_L3_HDL_OBJECT_DECLARED_NOT_USED" "READRAM LCD1602.v(52) " "Info (10035): Verilog HDL or VHDL information at LCD1602.v(52): object \"READRAM\" declared but not used" {  } { { "LCD1602.v" "" { Text "D:/Nailson/MCU/CPLD/AllTest/LCD1602.v" 52 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 1 0 "" 0}
{ "Info" "IVRFX_L3_HDL_OBJECT_DECLARED_NOT_USED" "cur_dec LCD1602.v(55) " "Info (10035): Verilog HDL or VHDL information at LCD1602.v(55): object \"cur_dec\" declared but not used" {  } { { "LCD1602.v" "" { Text "D:/Nailson/MCU/CPLD/AllTest/LCD1602.v" 55 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 1 0 "" 0}
{ "Info" "IVRFX_L3_HDL_OBJECT_DECLARED_NOT_USED" "cur_shift LCD1602.v(56) " "Info (10035): Verilog HDL or VHDL information at LCD1602.v(56): object \"cur_shift\" declared but not used" {  } { { "LCD1602.v" "" { Text "D:/Nailson/MCU/CPLD/AllTest/LCD1602.v" 56 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 1 0 "" 0}
{ "Info" "IVRFX_L3_HDL_OBJECT_DECLARED_NOT_USED" "shift_cur LCD1602.v(62) " "Info (10035): Verilog HDL or VHDL information at LCD1602.v(62): object \"shift_cur\" declared but not used" {  } { { "LCD1602.v" "" { Text "D:/Nailson/MCU/CPLD/AllTest/LCD1602.v" 62 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 1 0 "" 0}
{ "Info" "IVRFX_L3_HDL_OBJECT_DECLARED_NOT_USED" "right_shift LCD1602.v(63) " "Info (10035): Verilog HDL or VHDL information at LCD1602.v(63): object \"right_shift\" declared but not used" {  } { { "LCD1602.v" "" { Text "D:/Nailson/MCU/CPLD/AllTest/LCD1602.v" 63 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 1 0 "" 0}
{ "Info" "IVRFX_L3_HDL_OBJECT_DECLARED_NOT_USED" "datawidth4 LCD1602.v(66) " "Info (10035): Verilog HDL or VHDL information at LCD1602.v(66): object \"datawidth4\" declared but not used" {  } { { "LCD1602.v" "" { Text "D:/Nailson/MCU/CPLD/AllTest/LCD1602.v" 66 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 1 0 "" 0}
{ "Info" "IVRFX_L3_HDL_OBJECT_DECLARED_NOT_USED" "oneline LCD1602.v(68) " "Info (10035): Verilog HDL or VHDL information at LCD1602.v(68): object \"oneline\" declared but not used" {  } { { "LCD1602.v" "" { Text "D:/Nailson/MCU/CPLD/AllTest/LCD1602.v" 68 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 1 0 "" 0}
{ "Info" "IVRFX_L3_HDL_OBJECT_DECLARED_NOT_USED" "font5x7 LCD1602.v(70) " "Info (10035): Verilog HDL or VHDL information at LCD1602.v(70): object \"font5x7\" declared but not used" {  } { { "LCD1602.v" "" { Text "D:/Nailson/MCU/CPLD/AllTest/LCD1602.v" 70 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 1 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Create Symbol File 0 s 0 s Quartus II " "Info: Quartus II Create Symbol File was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "134 " "Info: Allocated 134 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 15 11:27:54 2009 " "Info: Processing ended: Thu Jan 15 11:27:54 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}