icunit_beschreibung.txt

这是一个由得到的命令(地址)从RAM 中读取命令并送入一个名为FUNREG的寄存器的代码,和前面的MINICORE 可以衔接,属于mikroprogrammbar steuerwerk(可编程的控制器

NAME
     icunit - Management of ICPRO design units

SYNOPSIS
     icunit [-OPTION] [-VIEW] [-HDL] <unit_name>

      -VIEW      : -rtl | -beh | -tb
      -HDL       : -verilog | -systemverilog | -sv | -vhdl | -vams | -systemc | -cdb | -ads
      -OPTION    : -h | -d | -noedit | -nosvn |
                    -parent=<unit_name>

     is used to create a new or child design unit of view VIEW
     and description language HDL.

     icunit [-OPTION] [-HDL] -dut=<unit_name> -tb
     <testbench_name>

     should be used to create an additional testbench
     <testbench_name> of unit <unit_name>.

DESCRIPTION
     Create ICPRO design units within projects "./unit"
     directory.  An ICPRO unit is a design block for which
     different tool steps could be executed.  The aim is to have
     all "unit" related sources and tool scripts centralized in
     one directory.  Every unit has a source directory, which
     could include different descriptions (views) of it as well
     as different HDL languages.  Also the source of a block-
     level testbench could be included there.  To structure the
     design database it is possible to place sub-modules, which
     are only relevant for this unit, in the source directory of
     the parent unit using option -parent=<unit_name>.

     If commandline parameters or unit name are ommited, a
     selection menu of required informations will be presented.

VIEWS
     -rtl    Create register transfer level (RTL) source file for
             design unit.  Files are placed in "./source/rtl/HDL"
             directory.

     -beh    Create behavioural level source file for design
             unit.  Source files are placed in
             "./source/behavioral/HDL" directory.

     -tb     Create testbench for design unit.  Source files are
             placed in "./source/tb/HDL" directory. Unlike -rtl
             and -beh, source files have default prefix "tb_". If
             -dut=<dut_name> is specified (2nd flavour of
             command) additional individually named testbenches
             may be created.




perl v5.8.0          Last change: 2008-09-05                    1






User Contributed Perl Documentation                     ICUNIT(1)



HDLS
     -verilog
             Create Verilog design unit, "unit_name.v".

     -systemverilog | -sv
             Create SystemVerilog design unit, "unit_name.sv".

     -vhdl   Create VHDL design unit, "unit_name.vhd".

     -vams   Create Verilog-AMS design unit, "unit_name.vams".

     -systemc
             Create SystemC design unit, "unit_name.cpp",
             "unit_name.h" .  Testbench HDL is determined by
             switch -vhdl or -verilog.

     -cdb    Create initial Cadence library in Cadence Data Base
             (cdb) format in "./cdslib/unit_name" directory of
             the unit for fullcustom design.  Level switch is not
             neccesary here. Command icunitcdb is a shortcut to
             create and initialize a new cdb unit (runs also
             icdf2 prepare, icdf2 makefile).

     -ads    Create initial Agilent ADS design environment unit.

OPTIONS
     -h|-help
             show extended manpage information

     -d|-debug
             show extended debugging information

     -noedit Usually a texteditor will be started after unit
             creation immediatly.  This switch suppresses
             starting of texteditor.

     -nosvn  Unit directories and sources will not be added to
             SVN repository in SVN controlled team projects

     -parent=<unit_name>
             Used to select parent unit to place new source files
             into.

     -dut=<unit_name>
             Used to select parent unit to place additional
             testbench files into.

EXAMPLES
     Create Verilog-RTL-description of an module named "adder"

         % iunit -rtl -verilog adder




perl v5.8.0          Last change: 2008-09-05                    2






User Contributed Perl Documentation                     ICUNIT(1)



     Create Cadence library (cdslib) of an fullcustom module
     named "fc_adc".

         % icunit -cdb fc_adc

     Create a testbench named "second_testbench" for design unit
     "adder".

         % icunit -dut=adder -verilog -tb second_testbench

REQUIRES


User Contributed Perl Documentation                     ICUNIT(1)



     Create Cadence library (cdslib) of an fullcustom module
     named "fc_adc".

         % icunit -cdb fc_adc

     Create a testbench named "second_testbench" for design unit
     "adder".

         % icunit -dut=adder -verilog -tb second_testbench

REQUIRES
     Perl 5.8

COPYRIGHT and LICENCE
      Copyright (c) 2005-2007.
      TU Dresden, IEE, HPSN