代码搜索：Verilog
找到约 10,000 项符合「Verilog」的源代码
代码结果 10,000
www.eeworm.com/read/109657/6173174
txt edit_mpf.txt
*****Copy the following line to the [vsim] section of your simulation.mpf.*****
Veriuser = $MG_LIB/mti_modelsim_verilog/libmgmm.so
www.eeworm.com/read/361329/6348228
qmsg dispselect.tan.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus
www.eeworm.com/read/493568/6395509
prj cpu.prj
verilog work "register.v"
verilog work "mux2.v"
verilog work "mux4.v"
verilog work "mux16.v"
verilog work "PC.v"
verilog work "SP.v"
verilog work "GR.v"
verilog work "ALU.v"
verilog work "MUL.
www.eeworm.com/read/490529/6447278
hif mux4.hif
Version 6.1 Build 201 11/27/2006 SJ Full Version
11
867
OFF
OFF
OFF
OFF
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
--
www.eeworm.com/read/490148/6459300
txt 目录.txt
目 录
译者序
前言
第1章 简介 1
1.1 什么是Verilog HDL？ 1
1.2 历史 1
1.3 主要能力 1
第2章 HDL指南 4
2.1 模块 4
2.2 时延 5
2.3 数据流描述方式 5
2.4 行为描述方式 6
2.5 结构化描述形式 8
2.6 混合设计描述方式 9
2.7 设计模拟
www.eeworm.com/read/181934/6466639
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity am29lv160d is
generic(
userpreload : integer := 1;
mem_file_name : string := "init.mem";
prot_file_name : string
www.eeworm.com/read/181934/6466643
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity vitalbuf is
port(
\OUT\ : out vl_logic;
\IN\ : in vl_logic
);
end vitalbuf;
www.eeworm.com/read/488254/6499965
qmsg seqdet.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 0
www.eeworm.com/read/488254/6500106
qmsg sys.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 0
www.eeworm.com/read/485465/6562822
prj seg7_display.prj
verilog work "div_clk_381hz.v"
verilog work "num_2bits.v"
verilog work "decod_2bits.v"
verilog work "mux4_1_4bits.v"
verilog work "rom_digits.v"
verilog work "seg7_display.v"