sys.map.qmsg

verilog hdl经典例程

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Full Version " "Info: Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed May 20 18:08:13 2009 " "Info: Processing started: Wed May 20 18:08:13 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off sys -c sys " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off sys -c sys" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "s_to_p.v(10) " "Warning (10273): Verilog HDL warning at s_to_p.v(10): extended using \"x\" or \"z\"" {  } { { "C:/altera/80/quartus/s_to_p.v" "" { Text "C:/altera/80/quartus/s_to_p.v" 10 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "C:/altera/80/quartus/sys.v 3 3 " "Info: Found 3 design units, including 3 entities, in source file C:/altera/80/quartus/sys.v" { { "Info" "ISGN_ENTITY_NAME" "1 p_to_s " "Info: Found entity 1: p_to_s" {  } { { "C:/altera/80/quartus/p_to_s.v" "" { Text "C:/altera/80/quartus/p_to_s.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "2 s_to_p " "Info: Found entity 2: s_to_p" {  } { { "C:/altera/80/quartus/s_to_p.v" "" { Text "C:/altera/80/quartus/s_to_p.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "3 sys " "Info: Found entity 3: sys" {  } { { "C:/altera/80/quartus/sys.v" "" { Text "C:/altera/80/quartus/sys.v" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "E:/lab/sys_tb.v " "Warning: Can't analyze file -- file E:/lab/sys_tb.v is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0 "" 0 0}
{ "Error" "EVRFX_VERI_FOUND_DUPLICATE_MODULE_DEFINITION" "p_to_s p_to_s.v(1) " "Error (10228): Verilog HDL error at p_to_s.v(1): module \"p_to_s\" cannot be declared more than once" {  } { { "sys/p_to_s.v" "" { Text "E:/lab/sys/p_to_s.v" 1 0 0 } }  } 0 10228 "Verilog HDL error at %2!s!: module \"%1!s!\" cannot be declared more than once" 0 0 "" 0 0}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "p_to_s p_to_s.v(1) " "Info (10151): Verilog HDL Declaration information at p_to_s.v(1): \"p_to_s\" is declared here" {  } { { "C:/altera/80/quartus/p_to_s.v" "" { Text "C:/altera/80/quartus/p_to_s.v" 1 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sys/p_to_s.v 0 0 " "Info: Found 0 design units, including 0 entities, in source file sys/p_to_s.v" {  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "s_to_p.v(10) " "Warning (10273): Verilog HDL warning at s_to_p.v(10): extended using \"x\" or \"z\"" {  } { { "sys/s_to_p.v" "" { Text "E:/lab/sys/s_to_p.v" 10 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "" 0 0}
{ "Error" "EVRFX_VERI_FOUND_DUPLICATE_MODULE_DEFINITION" "s_to_p s_to_p.v(1) " "Error (10228): Verilog HDL error at s_to_p.v(1): module \"s_to_p\" cannot be declared more than once" {  } { { "sys/s_to_p.v" "" { Text "E:/lab/sys/s_to_p.v" 1 0 0 } }  } 0 10228 "Verilog HDL error at %2!s!: module \"%1!s!\" cannot be declared more than once" 0 0 "" 0 0}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "s_to_p s_to_p.v(1) " "Info (10151): Verilog HDL Declaration information at s_to_p.v(1): \"s_to_p\" is declared here" {  } { { "C:/altera/80/quartus/s_to_p.v" "" { Text "C:/altera/80/quartus/s_to_p.v" 1 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sys/s_to_p.v 0 0 " "Info: Found 0 design units, including 0 entities, in source file sys/s_to_p.v" {  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Error" "EVRFX_VERI_FOUND_DUPLICATE_MODULE_DEFINITION" "sys sys.v(3) " "Error (10228): Verilog HDL error at sys.v(3): module \"sys\" cannot be declared more than once" {  } { { "sys/sys.v" "" { Text "E:/lab/sys/sys.v" 3 0 0 } }  } 0 10228 "Verilog HDL error at %2!s!: module \"%1!s!\" cannot be declared more than once" 0 0 "" 0 0}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "sys sys.v(3) " "Info (10151): Verilog HDL Declaration information at sys.v(3): \"sys\" is declared here" {  } { { "C:/altera/80/quartus/sys.v" "" { Text "C:/altera/80/quartus/sys.v" 3 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sys/sys.v 0 0 " "Info: Found 0 design units, including 0 entities, in source file sys/sys.v" {  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/lab/sys.map.smsg " "Info: Generated suppressed messages file E:/lab/sys.map.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 3 s 1  Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 3 errors, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "159 " "Error: Peak virtual memory: 159 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Error" "EQEXE_END_BANNER_TIME" "Wed May 20 18:08:14 2009 " "Error: Processing ended: Wed May 20 18:08:14 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:01 " "Error: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Error: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}