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Verilog 的代码
verilog.scr
/* link TOP design */
read COMPUTE_BLOCK.db
read CONVERTOR_CKT.db
read -format verilog TOP.v
current_design TOP
link
/* testability analysis */
set_test_hold 1 TEST_MODE
set_test_methodology full_sca
verilog.scr
/* optimize CONVERTOR_CKT */
read -format pla verilog/CONVERTOR.pla
read -format verilog verilog/CONVERTOR_CKT.v
current_design CONVERTOR_CKT
set_scan_style combinational
uniquify
compile
/* testabil
verilog.csh
#! /bin/csh
verilog -w -a -v library/verilog/class.v alarm_clock.v tb_alarm.v
awk -f verilog2tds.awk fnc.v > fnc.vec
dc_shell -f sdf.scr
.script_verilog
read -f pla verilog/CONVERTOR.pla
read -f verilog verilog/CONVERTOR_CKT.v
current_design CONVERTOR_CKT
link
set_scan_configuration -style combinational
uniquify
compile
check_test
create_test_pattern