verilog.scr

design compile synthesis user guide

/* link TOP design */
read COMPUTE_BLOCK.db
read CONVERTOR_CKT.db
read -format verilog TOP.v
current_design TOP
link

/* testability analysis */
set_test_hold 1 TEST_MODE
set_test_methodology full_scan
set_scan_style multiplexed_flip_flop
check_test
create_test_patterns -sample 11

report_test -atpg_conflict

current_design COMPUTE_BLOCK
remove_design COMPUTE_BLOCK
set_dont_touch find(design "*")
write find(design "*") -out save.db
remove_design find(design "*")

/* optimize COMPUTE_BLOCK with atpg conflict fix */
read -format verilog COMPUTE_BLOCK.v
read save.db
current_design COMPUTE_BLOCK
compile

/* verify atpg conflict is fixed */
current_design TOP
link
remove_attribute find(design "*") dont_touch
create_test_patterns -sample 11

/* generate nonscan area and timing reports */
create_clock CLK -period 15
report_area
report_timing

/* insert scan chain */
insert_test -no_disable

/* generate scan area and timing reports */
report_area
report_timing

/* incremental optimization */
compile -incr

/* generate optimized scan area and timing reports */
report_area
report_timing

/* verify no hold time violations */
create_clock CLK -period 100 -waveform {45 55}
set_clock_skew -propagated CLK
fix_hold all_clocks()
/* inputs are applied at time 5 */
set_input_delay -clock CLK -min -fall 1 all_inputs()
set_input_delay -clock CLK -min -rise 1 all_inputs()
report_constraints

/* generate and format manufacturing test patterns */
create_test_patterns
write_test -format wgl

/* save TOP design */
write -hier -out TOP.db
exit