代码搜索：Vector
找到约 10,000 项符合「Vector」的源代码
代码结果 10,000
www.eeworm.com/read/297458/8016511
vhd ddr_sdram_example_driver.vhd
--Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
--use of Altera Corporation's design tools, logic functions and other
--software and tools, and its AMPP partner logic functions,
www.eeworm.com/read/332097/12780867
vhd yuv.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
entity yuv is port(
y1,u,v,y2: in std_logic_vector(7 downto 0);
r1,g1,b1: out std_logic_
www.eeworm.com/read/139170/13185688
s vectors.s
/*********************************************************************
* File: vectors.s
* Purpose: MCF5200 vector table for dBUG.
*
*
* Copyright:
* 1999-2000 MOTOROLA, INC. All Rig
www.eeworm.com/read/138611/13228246
vhd display.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity display is
port ( CLK1: in STD_LOGIC;
CLK2 : in STD_LO
www.eeworm.com/read/324197/13279280
vhd top.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.commonConstants.all;
entity top is port(
clk, reset: in STD_LOGIC;
mem_enX, mem_rwX : out std_logic;
aBusX : out s
www.eeworm.com/read/324197/13279305
bak top.vhd.bak
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.commonConstants.all;
entity top is port(
clk, reset: in STD_LOGIC;
mem_enX, mem_rwX : out std_logic;
aBusX : out s
www.eeworm.com/read/137919/13279363
vhd display2.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity display2 is
port(din0: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
din1: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
www.eeworm.com/read/323369/13342507
vhd vhdl1.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY watch IS
PORT(clear:IN STD_LOGIC;
s1,m1:BUFFER STD_LOGIC_VECTOR(3 DOWN
www.eeworm.com/read/323369/13342509
vhd watch.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY watch IS
PORT(clear:IN STD_LOGIC;
s1,m1:BUFFER STD_LOGIC_VECTOR(3 DOWN
www.eeworm.com/read/323369/13342527
vhd watch_a.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY watch_a IS
PORT(clear,clk:IN STD_LOGIC;
s1,m1:BUFFER STD_LOGIC_VECTOR(