display2.vhd

程序用VHDL实现： 利用一秒定时测量频率 并且显示

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity display2 is
    port(din0: IN	STD_LOGIC_VECTOR (3 DOWNTO 0);
	     din1: IN	STD_LOGIC_VECTOR (3 DOWNTO 0);
  	     din2: IN	STD_LOGIC_VECTOR (3 DOWNTO 0);
	     din3: IN	STD_LOGIC_VECTOR (3 DOWNTO 0);
	     din4: IN	STD_LOGIC_VECTOR (3 DOWNTO 0);
	     din5: IN	STD_LOGIC_VECTOR (3 DOWNTO 0);
	     CLK:  IN   STD_LOGIC;
	
		
        LED_SA:	    out STD_LOGIC;  
		LED_SB:		out STD_LOGIC;  
		LED_SC:		out STD_LOGIC;
		LED_DP:		out STD_LOGIC;
		LED_SEG:     OUT STD_LOGIC_VECTOR(6 DOWNTO 0));  

		--LED_A:		out STD_LOGIC;  
		--LED_B:		out STD_LOGIC;  
		--LED_C:		out STD_LOGIC;  
		--LED_D:		out STD_LOGIC;  
		--LED_E:		out STD_LOGIC;  
		--LED_F:		out STD_LOGIC;  
		--LED_G:		out STD_LOGIC;  
		--LED_DP:		out STD_LOGIC );
end display2;

architecture behave of display2 is
	SIGNAL SEG: STD_LOGIC_VECTOR (6 DOWNTO 0);	
	SIGNAL SEL: STD_LOGIC_VECTOR (2 DOWNTO 0);	
	SIGNAL NUM: STD_LOGIC_VECTOR (3 DOWNTO 0);	
	signal s:std_logic_vector(2 downto 0);
	signal reg_hh:std_logic_vector(3 downto 0);
	signal reg_hl:std_logic_vector(3 downto 0);
	signal reg_mh:std_logic_vector(3 downto 0);
	signal reg_ml:std_logic_vector(3 downto 0);
	signal reg_sh:std_logic_vector(3 downto 0);
	signal reg_sl:std_logic_vector(3 downto 0);
begin
	led_sa<=sel(0);
	led_sb<=sel(1);
	led_sc<=sel(2);
	LED_SEG<=SEG;
	--led_a<=seg(0);
	--led_b<=seg(1);
	--led_c<=seg(2);
	--led_d<=seg(3);
	--led_e<=seg(4);
	--led_f<=seg(5);
	--led_g<=seg(6);

process(clk)
begin
	if clk'event and clk='1' then
          if s="101" then
	    s<="000";
	  else
	    s<=s+'1';
	  end if;
	end if;
end process;

process(s,din0,din1,din2,din3,din4,din5)
begin
	CASE s IS
		WHEN "000" => sel<="000"; num<=din0; led_dp<='0';
        WHEN "001" => sel<="001"; num<=din1; led_dp<='0';
        WHEN "010" => sel<="010"; num<=din2; led_dp<='0';
        WHEN "011" => sel<="011"; num<=din3; led_dp<='0';
        WHEN "100" => sel<="100"; num<=din4; led_dp<='0';
        WHEN "101" => sel<="101"; num<=din5; led_dp<='0';
        WHEN OTHERS =>sel<="111"; num<="1110"; led_dp<='0';
	END CASE;
	

end process;

SEG <= 	"0111111" WHEN NUM = 0 ELSE
 	"0000110" WHEN NUM = 1 ELSE
	"1011011" WHEN NUM = 2 ELSE
	"1001111" WHEN NUM = 3 ELSE
	"1100110" WHEN NUM = 4 ELSE
	"1101101" WHEN NUM = 5 ELSE
	"1111101" WHEN NUM = 6 ELSE
 	"0000111" WHEN NUM = 7 ELSE
	"1111111" WHEN NUM = 8 ELSE
	"1101111" WHEN NUM = 9 ELSE
	"1110111" WHEN NUM = 10 ELSE
	"1111100" WHEN NUM = 11 ELSE
	"0111001" WHEN NUM = 12 ELSE
	"1011110" WHEN NUM = 13 ELSE
	"1111001" WHEN NUM = 14 ELSE
	"1110001" WHEN NUM = 15 ELSE
	"0000000";
END BEHAVE;