display.vhd

来自「点阵显示实验示例使用说明 使用模块有：时钟源模块、点阵显示模块」· VHDL 代码 · 共 48 行

 library IEEE;
  use IEEE.std_logic_1164.all;
  use IEEE.STD_LOGIC_ARITH.ALL;
  use IEEE.STD_LOGIC_UNSIGNED.ALL;

  entity display is
    port ( CLK1: 		in STD_LOGIC;
	       CLK2 : 		in STD_LOGIC;
	      RESET: 		in STD_LOGIC;  
         LEDW: 	out STD_LOGIC_VECTOR (3 downto 0);
         A: 		out STD_LOGIC_VECTOR (7 downto 0));
  end display;

  architecture HAV of display is

   SIGNAL counter: std_logic_vector(3 downto 0);
    SIGNAL PAGE : INTEGER RANGE 0 TO 10;
    signal vv: std_logic_vector(2 downto 0);
    signal fp:std_logic;
      begin
     PROCESS(CLK2,RESET)
    BEGIN      
      IF RESET='1' THEN
      counter<="0000";
   elsif ( CLK2'event and CLK2='1') then 
      counter<=counter+1;
  end if;
          LEDW <=  counter;
   A(3 DOWNTO 0) <= counter;
   END PROCESS;
process(clk1)
begin
 if (clk1'event and clk1='1' ) then
    vv<=vv+1;
  end if;
 end process;
 fp<=vv(0);

   PROCESS(fp,PAGE)
   BEGIN
  If ( fp'event and fp='1') then 
		PAGE<=PAGE+1; 
	   		  END IF; 
   A(7 DOWNTO 4)<=conv_std_logic_vector(PAGE,4);
   END PROCESS;  
      END HAV;